Work Experience

08/06-04/11 Director of Technology, Chief Technology Office, AppliedMicro

  • Drive networking standards initiatives to meet product goals
  • Mentor senior management on technical and strategic directions
  • Build ecosystems for AppliedMicro’s new product initiatives
  • Expand AppliedMicro’s networking patent portfolio

11/05-08/06 Director of Advanced Technologies, Quake Technologies

  • Led standards initiatives for Quake’s physical layer products
  • Influenced senior management and lead architects on technical and strategic direction
  • Acquired by AppliedMicro in August 2006

11/02-11/05 Manager, Enterprise Interconnect Standards and Technology, Intel

  • Led standards team responsible for Ethernet and Fibre Channel
  • Provided strategic guidance and technical due diligence for multiple business units
  • Active participant with Intel Legal for patent harvesting and review
  • Created and built core team for the Ethernet Alliance incorporation and launch

01/00-10/02 Strategic Marketing Manager, LAN Access Division, Intel

  • Developed Intel’s Gigabit Ethernet and 10 Gigabit Ethernet roadmaps
  • Performed technical due diligence for Marvell Gigabit Ethernet LOM partnership
  • Provided architecture guidance to iSCSI development team

05/97-12/99 Senior ASIC Design Engineer, Jato Technologies/Level One Communications

  • Architected and coded physical layer interfaces for Gigabit Ethernet products
  • Provided critical guidance in timing analysis of the triple speed MAC controller silicon
  • Acquired by Level One Communications in 11/98, acquired by Intel in 12/99

06/93-02/97 ASIC Product Design Engineer, PMC-Sierra

  • Lead engineer on multi-person development team for LAN/WAN OC-3 ATM devices
  • Developed VHDL design and scan test methodologies

07/89-05/93 ASIC Design Engineer, Bell-Northern Research

  • Responsible for development of analog loop telephony controller devices for high-volume Maestro handset
  • Provided leadership, training and support to design team members